1. Field of the Invention
This invention relates to a process for forming integrated circuit structures with damascene structures having planarized upper surfaces. More particularly, this invention relates to a process for removal of excess portions of an electrically conductive diffusion barrier liner and a copper metallization filler layer on the upper surface of a dielectric layer having a damascene structure formed in and on the upper surface of the dielectric layer while inhibiting distortion and delamination of layers, and minimizing dishing and erosion effects in surfaces of copper interconnects formed using such damascene copper wiring structures lined with electrically conductive diffusion barrier material. In a preferred embodiment, the damascene wiring structure is formed in a layer of low k dielectric material.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of interconnects, including metal interconnects, being vertically placed closer together, as well as reduction of the horizontal spacing between metal lines on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH3—SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is then annealed to remove moisture. Such carbon-containing silicon oxide insulating materials formed in this manner, sometimes referred to as low k carbon-doped silicon oxide dielectric material, exhibit good gap-filling capabilities and at the same time are characterized by a dielectric constant less than 3.0 and remain stable during subsequent annealing at temperatures of up to 500° C.
Many of the same reasons for turning to the use of dielectric materials having lower dielectric constants, e.g., for increased performance, including speed, have also led to the increased use of copper instead of aluminum or tungsten in the formation of metal interconnects, as well as via filler material, for integrated circuit structures.
But there are negative aspects to the choice of copper as the trench and/or via filler material in the formation of metal lines. Copper, when placed in direct contact with a dielectric layer, particularly a layer of low k dielectric material, will migrate into the dielectric material, thus necessitating the formation of a diffusion barrier liner between the copper filler and the dielectric layer.
Furthermore, while a layer of aluminum interconnects may be easily formed by depositing a layer of aluminum metal over a dielectric layer of an integrated circuit structure, followed by patterning of the aluminum layer through a mask to form aluminum interconnects, and subsequent deposition of dielectric material in the spaces between the metal interconnects, layers of copper interconnects are not so easily formed. This is due to difficulty in patterning (etching) of a previously deposited copper layer. This has lead to the development of processes commonly known as single damascene or dual damascene processes.
In the damascene processes the dielectric material which will separate the copper interconnects is first deposited as one or more dielectric layers in which trenches are then formed in the uppermost dielectric layer (usually through the entire thickness of the dielectric layer), corresponding to the desired pattern of copper interconnects. When a single damascene structure is desired, one or more electrically conductive barrier liner layers are then formed over the trench surfaces (as well as over the top surface of the dielectric layer), and a layer of copper is then deposited over the patterned dielectric layer and into the lined trenches, filling them completely. All surface copper is then removed, conventionally by a chemical mechanical polishing (CMP) process, followed by removal of surface portions of the barrier liner also using a CMP process, leaving the desired pattern of copper interconnects in the trenches, with the remaining portions of the dielectric layer forming the insulation between the copper interconnects.
In the formation of a dual damascene structure, the above process is modified to add a step comprising the formation of openings (vias) in a lower dielectric layer, usually in registry with trench openings formed in an upper dielectric layer. Both the via and trench openings are then lined with barrier material as described above, and then a blanket layer of copper is formed over the top surface of the upper layer of dielectric material, which fills both the vias and the trenches with copper, usually in a single deposition step.
While the use of copper-filled vias and copper interconnects, formed in one or more layers of low k carbon-doped silicon oxide dielectric material by the dual damascene process, has been found to be useful in reducing capacitance and increasing speed of integrated circuit structures utilizing such constructs, the conventional prior art chemical mechanical polishing (CMP) process used to remove the excess copper and barrier material from the upper surface of the top dielectric material to planarize the structure and to prevent shorts, also results in erosion and/or dishing of the copper in the trenches as the excess copper and barrier liner material is removed.
Prior art FIGS. 1-4 illustrate the problems of erosion and dishing of the copper. FIG. 1 show a typical dual damascene structure formed over an integrated structure generally indicated at 2 comprising a layer 4 of dielectric material and electrically conductive portions 6 comprising lower level metal interconnects or filled vias, or filled contact openings. The dual damascene structure comprises a lower dielectric layer 10 having vias 14 formed therethrough and an upper dielectric layer 20 with trenches 24 formed therein in registry with vias 14. An electrically conductive barrier liner 30 is shown lining the exposed surfaces of vias 14 and trenches 24 and extending over the upper surface 26 of upper dielectric layer 20. A copper filler layer 40 is shown filling the lined vias 14 and lined trenches 24 and extending over the upper surface of those portions of underlying barrier liner 30 on upper surface 26 of upper dielectric layer 20.
Prior art FIG. 2 shows the structure of FIG. 1 after the structure has been subjected to a conventional prior art chemical mechanical polishing (CMP) step to remove all of copper layer 40 on the surface of those portions of barrier liner 30 formed over the upper surface 26 of upper dielectric layer 20, with those portions of barrier layer 30 on upper surface 26 of dielectric layer 20 yet to be removed.
Prior art FIGS. 3 and 4 show the structure of FIG. 2 after removal of all of barrier liner 30 on upper surface 26 of dielectric layer 20. FIG. 3 illustrates, at 42, the problem of erosion of the surface of the copper in the trench caused by the CMP process used in the removal of those portions of copper layer 40 and barrier liner 30 lying on upper surface 26 of dielectric layer 20, while FIG. 4 shows, at 44, the problem of dishing of the surface of the copper in the trench also caused by the same CMP process. It should be noted that while the problems of erosion and dishing have been shown separately in FIGS. 3 and 4, for illustrative purposes, both problems may occur in the same integrated circuit structure, depending upon the width of the particular copper line.
Furthermore, the conventional prior art chemical mechanical polishing (CMP) process used to remove the excess copper and barrier material from the upper surface of the top dielectric material and to planarize the structure, can also promote defects in the layer or layers of such low k dielectric materials such as cracks and/or delamination, due to the wafer pressure and the sheer strength of the polishing process. Sometimes even though the low k dielectric film makes it through the CMP process without cracking, the low k dielectric film may crack during later processing due to the stresses created during the CMP processing.
Delamination can occur between the low k dielectric layer and the diffusion barrier liner, as well as between the diffusion barrier liner and the copper layer. This failure mode may be experienced to some degree whenever the damascene process is employed with subsequent CMP processing then used to remove the portions of the copper layer and the diffusion barrier liner remaining on the upper surface of the insulation material.
Delamination or distortion at these interfaces can produce weakness and defects in the barrier liner layer or film which can result in electromigration failures and in failure of the copper diffusion barrier liner to act as a barrier. Diffusion of copper through defects in the diffusion barrier liner can result in electrical failure through electrical leakage and shorts, and to contamination of the underlying transistors.
Prior art FIGS. 5-6 illustrate the problems of distortion and delamination in general, using a dual damascene structure to demonstrate these problems. FIG. 5 show a typical dual damascene structure formed over an integrated structure generally indicated at 2, prior to removal of excess material used to line and fill the vias and trenches in the dual damascene structure. The dual damascene structure comprises a lower dielectric layer 10 having a via 12 formed therethrough, an etch stop layer 16, and an upper dielectric layer 20 with a trench 22 formed therein in registry with via 12. An electrically conductive diffusion barrier liner 30 is shown lining the exposed surfaces of via 12 and trench 22 and extending over the upper surface 26 of upper dielectric layer 20. A copper filler layer 40 is shown filling lined via 12 and lined trench 22 and extending over the upper surface of those portions of underlying diffusion barrier liner 30 on the upper surface 26 of upper dielectric layer 20.
Prior art FIG. 6 shows the structure of FIG. 5 after the structure has been subjected to a conventional prior art chemical mechanical polishing (CMP) step to remove all of copper layer 40 on the surface of those portions of diffusion barrier liner 30 formed over the upper surface 26 of upper dielectric layer 20, and with those portions of diffusion barrier layer 30 on upper surface 26 of dielectric layer 20 also removed by a CMP process, leaving only diffusion barrier liner 30a and copper filler 40a in via 12 and trench 22.
It will be noted that delamination is shown in FIG. 6 (in exaggerated form for illustrative purposes) at 34 between trench 22 in low k dielectric layer 20 and diffusion barrier liner 30a; and also at 44 between diffusion barrier liner 30a and copper filler 40a. As mentioned above, such delamination at these interfaces can produce weakness and defects in the barrier liner film which can result in electromigration failures and in failure of the diffusion barrier liner to act as a diffusion barrier to prevent copper migration. This can result in diffusion of copper through such defects in the diffusion barrier liner layer which can, in turn, result in electrical failure through electrical leakage and shorts, and to contamination of the underlying transistors.
All of the problems just discussed are further exacerbated by the fact that all of top portions 30a of barrier liner 30, shown in FIG. 2, must be removed from surface 26 of dielectric layer 20, since barrier liner 30 comprises an electrically conductive material and failure to remove all of the surface portions 30a of barrier liner 30 would result in electrical shorts between adjacent metal interconnects comprising copper-filled trenches 24.
Ference et al. U.S. Pat. No. 6,221,775 teach a process of planarizing the surface of a dielectric layer on a semiconductor substrate having raised and recessed regions on the surface of the dielectric layer as a resulting of the forming and filing of trenches and vias in the dielectric layer. An etch stop or “polish stop” layer is first formed over the patterned raised and recessed regions, and (optionally) a barrier layer is then deposited over all of the underlying surfaces, including the surfaces of the trenches and vias and the upper surface of the dielectric layer. A layer of metal such as tungsten, copper, or aluminum is then deposited over the barrier layer to a thickness sufficient to completely fill the trenches and/or vias. The resulting stack is then subject to two planarization steps, the first of which is a chemical mechanical polishing (CMP) process, and the second of which is said to be a reactive ion etch (RIE).
The Ference et al. '221 patent describes three embodiments for carrying out their two step process. In the first embodiment, the stack is subject to a CMP process to planarize it, but the step of planarization by CMP is stopped before any exposure of the liner, and the planarization is then completed by the RIE step. In the second embodiment, the CMP process is again used but the slurry in the CMP process is selective to the liner, i.e., the material in the conductive layer etches at a faster rate than the liner material. The CMP process in this embodiment is stopped after removing all excess conductor material, but before removing all of the excess liner. In both embodiments, all remaining liner, as well as any remaining conductor, are removed using RIE. In a third embodiment, a traditional CMP process is performed to remove both the liner and conductive layers and to thereby expose the surface of the underlying dielectric layer. A touch-up CMP process is then performed to remove scratches as necessary. Then the RIE step is applied to remove metal in eroded regions of prior scratches.
Wang U.S. Pat. No. 6,440,295 describes an electropolishing apparatus for polishing a metal layer formed on a wafer (31) and includes an electrolyte (34), a polishing receptacle (100), a wafer chuck (29), a fluid inlet (5, 7, 9), and at least one cathode (1, 2, 3). The wafer chuck (29) holds and positions the wafer (31) within the polishing receptacle (100). The electrolyte is delivered through the fluid inlet into the polishing receptacle. The cathode then applies an electropolishing current to the electrolyte to electropolish the wafer. In accordance with one aspect of the present invention, discrete portions of the wafer can be electropolished to enhance the uniformity of the electropolished wafer. Wang further teaches the use of a chemical-mechanical polishing (CMP) process to remove remaining portion of the metal (copper) layer and the underlying electrically conductive barrier layer. Wang also states that in substitution for use of the CMP process for the removal of the remainder of the excess copper layer and layer of electrically conductive, one may etch away the remaining metal layer and barrier layer using any convenient etching process.
Chung U.S. Pat. No. 6,395,607 describes a microelectronic device wherein a trench having inside walls is formed through a dielectric layer. A lining of a barrier metal is deposited on the inside walls of the trench, and the lined trench is then filled with a fill metal. The fill metal and the barrier metal are said to have substantially different removal selectivities. After filling the trench with the fill metal, excess portions of the fill metal over the top surface of the dielectric layer are then removed with a conventional etch such as a chemical/mechanical/polishing etch (CMP) etch.
Chung then forms a recess or dished portion in the end of his fill metal. Chung states that the this recess may be formed by a proper combination of chemical mechanical polishing (CMP), plasma etch, wet etch, or electropolishing, without identifying what this combination might be. A further layer of the barrier metal is then deposited over the first barrier metal layer and filing up the recess, thereby completely encapsulating the fill metal. The excess barrier metal is then removed from over the top of the dielectric layer by chemical mechanical polishing (CMP), plasma etching, wet etch, or electropolishing.
It would, however, be desirable to provide a process wherein copper interconnects and copper-filled vias could be formed in dielectric material, including low k carbon-doped silicon oxide dielectric material, while inhibiting or eliminating the problems of dishing/erosion of the surface of copper filler material in the trenches during removal of surface portions of the barrier liner material and planarizing of the structure, as well as the problems of distortion and delamination of the layers due to the planarization methods used to remove the excess copper filler material and electrically conductive liner material.